A programmable analogue spiking neural network chip, built from discrete off-the-shelf components. Its analogue core classifies digits at microjoules per inference: three orders of magnitude below the digital overhead on the same task.
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Every neuron fires, every connection computes. All at once, every cycle.
A smooth, continuous stream of numbers, always flowing.
A rigid clock. Everything in lockstep.
Like leaving every light in a building on to read one book.
Only active neurons fire. The rest stay silent.
Sharp spike, only when something happens. Silence is information.
No clock. neurons respond when events arrive.
Like the brain: billions of neuron, only a fraction active at any moment.
Each of the 19 neurons on the board is a real RC circuit implementing the leaky integrate-and-fire (LIF) model: charge up, leak away, fire at threshold, reset. The equation isn't numerically approximated — it's soldered.
Weighted synaptic currents charge a 10 nF membrane capacitor. Multiple inputs sum for free via Kirchhoff's current law — no adder circuit exists.
A parallel 120 kΩ resistor drains the capacitor with τm = RC = 1.2 ms. Exponential decay makes the neuron forget old inputs — timing becomes information.
When the membrane crosses threshold (0.60 V hidden, 1.15 V output), an LMV7219 comparator fires a spike, stretched by an RC pulse extender so it can drive the next layer.
An analog switch (SN74LVC1G66) pulls the membrane back to rest, with a hysteresis network adding breathing room against double-fires.
The project's novel contribution: a fully programmable analogue synapse with no variable-resistance element. As best as the team can tell, it is the first fully programmable analogue spiking synapse array demonstrated at this scale on a single discrete-component PCB.
A reference current (~0.435 µA) is copied by matched BJT current-mirror banks — ×1, ×2, ×4 — switched in and out by a shift register. Weight magnitude is which mirrors are enabled.
A sign bit routes through either the PNP bank (excitatory, injects charge) or the NPN bank (inhibitory, drains it). Result: signed integer weights in {−7 … +7} — 1 sign bit, 3 magnitude bits.
Current flows onto the downstream membrane only while an upstream spike is asserted. Multiply-accumulate collapses to a gated current — the multiply is just a switch.
~25 discrete parts per synapse on the demo board. In silicon, the identical function maps one-to-one onto a single floating-gate transistor — the discrete design is a deliberate proof of concept for that ASIC path.
Designing analogue hardware means simulating real physics. SPICE takes ~75 seconds per inference at default tolerances — half an hour at the full physics horizon. Training needs millions of forward passes. Gilgamesh makes that possible.
One MNIST inference through the 36-12-10 spiking neural network, on the same laptop.
Training requires millions of these forward passes. A single forward-only epoch in SPICE is ~52 days of wall clock, and SPICE cannot train at all. Gilgamesh does 15 full epochs in under six seconds.
We validated the architecture in simulation, end to end. The 36-9-10 demo board is now populated and under test — physical spikes from physical neurons, coming back from the oscilloscope. End-to-end MNIST on the board at the predicted accuracy is the current bring-up goal.
Handwritten digits fed as rate-coded currents, classified by counting output spike. Through the full emulated board round-trip — real firmware, real schematic, real part tolerances — the pipeline holds 85.1%, settling at 83.4 ± 0.4% across ten virtual manufacturing draws.
The demo board implements a 36-9-10 network: 36 inputs (6×6 pixels), 9 hidden LIF neuron, 10 outputs. 414 logical synapses compress to 99 physical ones via DAC-driven input current sources; the 90 hidden-to-output synapses are fully independent current-mirror weights.
The analogue core uses ~7.4 microjoules per inference (emulator estimate), roughly three orders of magnitude below the digital overhead on the same 25 ms window. The board as built draws ~141 mW, at parity with the 140 mW Arduino baseline; one conservative comparator choice accounts for 74% of that, and a drop-in swap projects ≈37 mW.
A 6×6 pixel image goes in as rate-coded current. spikes come out. The neuron that fires most wins. The analogue core runs on microjoules.
ECG traces are temporally rich, low-dimensional, and a natural fit for a rate-coded SNN. The training pipeline already supports time-varying streams — this is the named near-term application target.
Anomaly detection that sips power. A nano-power comparator swap drops the board to ≈37 mW; the planned sub-1.2 V successor projects into single-digit milliwatts.
Each ~25-part discrete synapse maps one-to-one onto a single floating-gate transistor. Trained weights transfer directly — the board is a working proof of concept for the ASIC.
MNIST handwritten digit classification is the standard benchmark for proving AI hardware feasibility. These results validate that Tarski's analogue circuits can learn and classify; they are not a production deployment target. All figures are simulation/emulator; board-measured accuracy is the current bring-up goal.
| Architecture | Image | synapse | Mode | Accuracy | |
|---|---|---|---|---|---|
| 24-6-10 | 3×8 | 204 | Full precision (f32) | 80.06% | |
| 36-9-10 | 6×6 | 414 | Full precision (f32) | 89.34% | |
| 36-12-10 | 6×6 | 552 | Full precision (f32) | 91.38% | F32 BEST |
| 36-9-10 | 6×6 | 414 | 3-bit QAT + noise | 87.4% | BOARD CONFIG |
| 36-9-10 | 6×6 | 414 | Emulated board round-trip | 85.1% | |
| 36-9-10 | 6×6 | 414 | 10-board mismatch draws | 83.4 ± 0.4% |
14,600 lines of Rust. Surrogate-gradient training fused into a single compiled kernel: 15 MNIST epochs in 4.87 seconds on a laptop CPU, 3-bit quantisation-aware, with noise injection matched to real component tolerances — and validated against SPICE spike-for-spike.
The 350 × 350 mm four-layer PCB came back from JLCPCB pre-assembled: 3,442 components, every neuron, comparator and synapse mirror bank already mounted. Bring-up was a genuine resurrection — three stacked power faults peeled back one by one (90 hand-cut traces among them), a threshold rework across all 19 neurons, and the pulse-extender fix the emulator prescribed before the board ever reached the bench. It now powers cleanly: we're driving inputs, capturing spikes on the scope, and verifying the hardware behaves the way Gilgamesh said it would.
Third-year EEE student at University of Galway. Designed the neuron and synapse circuits, built the Gilgamesh simulator and the hardware-accurate board emulator, and wrote the training pipeline. Runs Eltrus Limited, a medical software company serving 400+ patients.
Hardware co-designer on the 3,442-component PCB. Led the board layout and routing, built the small-scale prototypes and the Arduino digital baseline, and wrote the oscilloscope measurement suite.